Systems and methods for single-molecule detection using nanopores

ABSTRACT

A system and method for detecting a single-molecule using an integrated circuit which includes at least one membrane having a nanopore located between first and second reservoirs and a low-noise preamplifier having an electrode formed on the surface thereof is provided. The method includes passing a target molecule through the nanopore, and measuring a current through the nanopore to detect the presence of a biomolecular entity, if any.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No.PCT/US2012/026292, filed Feb. 23, 2012, which claims priority to U.S.Provisional Patent Application No. 61/445,918, filed Feb. 23, 2011, eachof which is incorporated by reference herein in its entirety.

BACKGROUND

The disclosed subject matter relates to the detection ofsingle-molecules. There is demand for DNA sequencing systems to besingle-molecule, massively parallel, and real-time. For single-moleculeoptical techniques, however, the signal from a single fluorophore can be<2500 photons/sec (equivalent to electrical current levels on the orderof 50 fA). This can lead to complex optics to try to collect everyphoton emitted and makes scaling of the platforms difficult. Conversely,relevant chemical reactions can be intentionally slowed to 1 Hz (orslower) to allow sufficient imaging times for these weak, noisy opticalsignals.

In contrast, electrochemical detection approaches, can havesignificantly higher signal levels (often several orders of magnitudestronger), allowing for high-bandwidth detection with the appropriateco-design of transducer, detector, and amplifier. Nanopore technology isone potential bioelectronic transduction mechanism. Nanopores, however,can be limited by the relatively short time biomolecules spend in thecharge-sensitive region of the pore. Restricted by the use ofoff-the-shelf electronics, the noise-limited bandwidth of nanoporemeasurements is typically less than 100 kHz, limiting the availablesensing and actuation strategies and defying multiplexed integrationwhich would be required for any sequencing application.

SUMMARY

Disclosed herein are new and improved systems and methods forsingle-molecule detection using nanopores.

The disclosed subject matter provides single-molecule detection andanalysis based on the electrochemical conductance modulation of asolid-state or biological nanopore sensor including a low-noisemulti-channel micro-scale preamplifier with integrated microelectrodes.In one embodiment, the nanopore sensor includes a low-noisemulti-channel CMOS preamplifier with integrated microelectrodes.

In some embodiments, the microelectrodes can be on-diesilver/silver-chloride (Ag/AgCl) microelectrodes. For example, a“two-chip” solution in which the pore and measurement electronics are onseparate adjacent dice can be used, or a “one-chip” solution in whichthe pore is directly integrated on the substrate containing themeasurement electronics can be used. In some embodiments, the surface ofthe preamplifier is exposed to one of the electrolyte reservoirs.

Monolithic integration of solid-state nanopores in an amplifier chip isalso provided. Reduced parasitic capacitances (e.g., less than 1 pF) canbe provided by integration of nanopores in silicon nitride membranes orgraphene membranes onto the same chip as the measurement electronics, toprovide more complete characterization of the high-frequency electronicproperties of the nanopore.

In another embodiment, a method for detecting a single molecule using anintegrated circuit which includes at least one membrane having ananopore located between first and second reservoirs and a low-noisepreamplifier having an electrode formed on the surface thereof isprovided. The method includes passing a target molecule through thenanopore, and measuring a current through the nanopore to detect thepresence of a biomolecular entity, if any.

In some embodiments, the preamplifier comprises a low-noisemulti-channel CMOS preamplifier. The electrode can be created from arange of materials including Ag/AgCl, platinum, gold, and un-chlorinatedsilver.

In some embodiments, the nanopore is positioned on a silicon chipadjacent to the preamplifier. Alternatively, the nanopore comprises ananopore directly integrated through the preamplifier. Is such anembodiment, the first and second reservoirs can be located on oppositesides of the preamplifier.

In some embodiments, the nanopore can comprise a solid state nanopore ora biological nanopore. The membrane can be a lipid bilayer. Theintegrated circuit can comprise a plurality of nanopores.

In some embodiments, the integrated circuit further comprises a ballgrid array and a printed circuit board.

In another embodiment, an integrated circuit for single-moleculedetection is provided. The integrated circuit comprises at least onemembrane having a nanopore located between first and second reservoirsand a low-noise preamplifier for measuring the change in pore currentupon passing a target entity through the nanopore. The preamplifier hasat least one electrode formed on the surface thereof.

The accompanying drawings, which are incorporated and constitute part ofthis disclosure, illustrate certain embodiments of the disclosed subjectmater and serve to explain its principles.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features, the nature, and various advantages of the disclosedsubject matter will be more apparent from the following detaileddescription of the embodiments and the accompanying drawings in which:

FIG. 1 is a graphical representation of the electronic impedances of asolid-state nanopore chip in accordance with some embodiments of thedisclosed subject matter;

FIG. 2 is a electrical model of a voltage-clamp current preamplifier inaccordance with some embodiments of the disclosed subject matter;

FIG. 3 is a graph of the typical spectral density of nanoporemeasurement noise in accordance with some embodiments of the disclosedsubject matter;

FIG. 4 is a illustration of the types of current pulses which resultfrom single-molecule interactions with nanopores in accordance with someembodiments of the disclosed subject matter;

FIGS. 5A-5F each is a graphical representation of the compact nanoporemeasurement platform in accordance with some embodiments of thedisclosed subject matter;

FIGS. 6A-6B are schematics of the preamplifier circuit topology inaccordance with some embodiments of the disclosed subject matter;

FIG. 7 is a circuit design of the low-noise current source whichsubstitutes for a feedback resistance in accordance with someembodiments of the disclosed subject matter;

FIGS. 8A-8D are images of the fabrication of on-chip electrodes inaccordance with some embodiments of the disclosed subject matter;

FIG. 9 is a schematic of a two-chip stacked measurement cell inaccordance with some embodiments of the disclosed subject matter;

FIG. 10 is graph of the transient measurements of DNA molecules passingthrough a nanopore in accordance with some embodiments of the disclosedsubject matter;

FIG. 11 is a local cross section schematic of a post-fabricated siliconnitride membrane in accordance with some embodiments of the disclosedsubject matter;

FIG. 12 is a series of die photographs showing an integrated nanopore inaccordance with some embodiments of the disclosed subject matter;

FIG. 13 is a graph of the measured and simulated input-referred noise inaccordance with some embodiments of the disclosed subject matter;

FIG. 14 is diagram of a single-chip packaging in accordance with someembodiments of the disclosed subject matter;

FIG. 15 is graph of DNA translocation through a nanopore sensor inaccordance with some embodiments of the disclosed subject matter;

FIG. 16 is graph of the nanopore input-referred noise verses measurementbandwidth in accordance with some embodiments of the disclosed subjectmatter;

FIG. 17 is graph of the noise-limited bandwidth in accordance with someembodiments of the disclosed subject matter;

FIG. 18 is diagram of a single chip packaging having multiple nanoporesin accordance with some embodiments of the disclosed subject matter;

FIG. 19 is diagram of a two-chip packaging having multiple nanopores inaccordance with some embodiments of the disclosed subject matter;

FIGS. 20A-20C each is a diagram of building lipid bilayers on thesurface of a CMOS-integrated nanopore platform (CNP) design inaccordance with some embodiments of the disclosed subject matter.

FIGS. 21A-21I each shows graphs of the current noise measurements inaccordance with some embodiments of the disclosed subject matter;

FIG. 22 is a continuous trace recorded for 25 bp dsDNA fragments for apore (i.e. PoreB) using a CNP platform at a bias of 600 mV in accordancewith some embodiments of the disclosed subject matter;

FIGS. 23A-23D each shows a collection of events showing the impact ofhigher measurement bandwidth on the quality of statistics gathered fornanopore sensors in accordance with some embodiments of the disclosedsubject matter; and

FIGS. 24A-24D each is a presentation of intra-event structure observedwith short oligomers and small nanopores in accordance with someembodiments of the disclosed subject matter.

Throughout the drawings, the same reference numerals and characters,unless otherwise stated, are used to denote like features, elements,components or portions of the illustrated embodiments. Moreover, whilethe present disclosed subject matter will now be described in detailwith reference to the Figures, it is done so in connection with theillustrative embodiments.

DETAILED DESCRIPTION

New and improved techniques are provided for single-molecule detectionutilizing nanopore sensors. The present disclosure provides forsignificant reduction in input capacitance and improved noiseperformance, an improvement in the noise-limited bandwidth of thedetection electronics for nanopores, a reduction in physical size, andincreased throughput by utilizing parallelized nanopore measurements.

Nanopore sensors are single-molecule electrochemical systems in whichtwo electrolyte reservoirs (i.e. aqueous salt buffers) are separated bya membrane containing a single nanoscale pore. Electrodes are placed ineach of the reservoirs, and by establishing an electrical voltagegradient between the chambers, charged molecules can be induced to passthrough the pore, with the presence of a molecule resulting in atransient change in the pore's electrochemical conductance. The measuredelectrical current corresponds to the transport of dissolved ionsthrough the pore, and when a molecule, such as DNA, passes through thepore, there is a transient change in the ionic current. There are atleast two attributes of this electronic sensor that give itsingle-molecule sensitivity. The first is the localized (nanoscale)geometry of charge sensitivity in the pore itself. The diameter d of apore can be 1-10 nm, and due to electrolyte charge screening themeasured current is highly insensitive to charge sources more than a fewnanometers from the pore. The second attribute of nanopores is theirhigh sensitivity, achieved by using high-mobility salt ions to infer thepresence of a comparatively slow-moving biomolecule.

Analysis of bandwidth in nanopore sensing systems is similar to theanalysis of voltage-clamp electrophysiology recordings, except that themagnitudes of contributing elements can vary significantly. Becausethese systems produce weak transient signals, their useful signalbandwidths are generally constrained not by small-signal frequencyresponse but by the signal-to-noise ratio (SNR). Detailed treatments ofnoise in ion channel recordings often address scenarios with signalamplitudes of 10 pA or less, for which relevant bandwidths are typicallyless than 10 kHz. However, nanopore sensors often use more concentratedelectrolytes and higher holding potentials, producing current pulses of100 pA from alpha-Hemolysin, 300 pA for MspA, and upwards of 4 nA forsolid-state nanopores.

A nanopore can be modeled as an ionic resistance R_(P) in series with anaccess resistance R_(A), along with a shunt capacitance C_(M) from thesupporting membrane structure, as shown in FIG. 1. In addition,capacitance is associated with the electrode wiring (C_(W)), theamplifier input stage (C_(I)), and the amplifier feedback elements(C_(FB)). An electrical circuit equivalent of this arrangement is shownin FIG. 2.

The noise spectrum of nanopore current measurements has several distinctregions, as illustrated in FIG. 3 for the purpose of illustration. Atlow frequencies (<100 Hz), 1/f noise and Johnson noise from the poreconductance is present. At moderate frequencies (100 Hz-10 kHz) sourcesof white noise in the pore or measurement electronics can appear, alongwith thermal noise generated by lossy dielectric materials (FIG. 3). Athigher frequencies (>10 kHz), the dominant noise source is theinteraction between the amplifier's voltage noise with the totalcapacitance present at the input node. In this regime the input-referrednoise spectral density scales with i_(n) ²≈(2πfC)²*e_(n), where e_(n) isthe equivalent input voltage noise power of the amplifier. The value Cis the sum of several distinct physical capacitances: the thin membranein which the nanopore is fabricated acts as a capacitor between thefirst and second (i.e. cis and trans) reservoirs; stray capacitances canbe present in any wiring between the electrodes and the amplifier; andthe amplifier itself will have a characteristic capacitance at itsinput. The membrane capacitance can be the largest of these threeelements, contributing as much as several hundred picofarads. However,that noise can be significantly reduced by limiting the fluid contactarea with the chip, or by passivating the surface of the chip with athick dielectric. As the membrane capacitance (C_(MEMBRANE)) reduces,the attention turns to the reactance of the electrode wiring andamplifier input. Certain known electrophysiology amplifiers typicallyhave an input capacitance (C_(IN)) on the order of 15 pF, and a wiringcapacitance (C_(WIRING)) of several picofarads is not unreasonable,which can limit the abilities of the nanopore sensor.

In further detail, the input-referred power spectral density is:

S _(n) ²(f)≈[2πf(C _(M) +C _(W) +C _(I) +C _(FB))v _(n)]²  (1)

and root-mean-squared noise is given by:

$\begin{matrix}{{I_{RMS}(B)} \approx {\frac{2\; \pi}{\sqrt{3}}{B^{\frac{3}{2}}\left( {C_{M} + C_{W} + C_{I} + C_{FB}} \right)}v_{n}}} & (2)\end{matrix}$

where v_(n) is the voltage noise density (V/√Hz) of the input amplifierand B is the measurement bandwidth.

For purposes of arriving at a signal-to-noise (SNR) metric, previouslythe signal level has been defined as ΔI, the average change in currentcaused by the presence of a molecule in the pore. The corresponding SNR,which is a function of the measurement bandwidth, is given byΔI/I_(RMS)(B). While this is a useful expression, it neglects the factthat the signals themselves are also filtered by the choice ofmeasurement bandwidth. To more accurately evaluate performance when thesignal content exceeds the available bandwidth, the SNR is insteaddefined as:

$\begin{matrix}{{{SNR}\left( {B,\tau} \right)} = {\frac{\Delta \; I}{I_{RMS}(B)}\frac{1}{\sqrt{1 + \frac{1}{2\; B\; \tau}}}}} & (3)\end{matrix}$

where τ is the minimum duration of the signals of interest as shown inFIG. 4 for the purpose of illustration. A consequence of thismodification is that the SNR does not necessarily decrease withmeasurement bandwidth. If a signal contains brief transient events, SNRcan increase for wider bandwidths despite higher I_(RMS) values.

Combining these expressions, the maximum bandwidth (B_(MAX)) whichmaintains an acceptable signal-to-noise ratio (SNR_(MIN)) can bedefined. If τ<100 μs and B>>½τ, this upper bound on the measurementbandwidth is given by:

$\begin{matrix}{B_{MAX} \approx \left\lbrack \frac{\Delta \; I\sqrt{3}}{{SNR}_{MIN} \times 2\; {\pi \left( {C_{M} + C_{W} + C_{I} + C_{FB}} \right)}v_{n}} \right\rbrack^{\frac{2}{3}}} & (4)\end{matrix}$

It is clear that the available bandwidth B_(MAX) increases for largersignal levels (ΔI) and decreases for larger capacitances and amplifiervoltage noise. All of the capacitances in this expression are extrinsicto the nanopore and, therefore, eligible for improvement withoutaffecting the properties of the pore itself.

In accordance with one aspect of the disclosed subject matter, aCMOS-integrated nanopore platform (CNP) is based around a low-noisecurrent preamplifier and a high-performance solid-state nanopore or abiological nanopore (as described further below). The preamplifiercircuitry can occupy 0.2 mm² in a 0.13 μm mixed-signal CMOS process andis positioned directly within the fluid chamber, as shown in FIGS.5A-5F. In one embodiment, a thin silicon nitride nanopore, designed withhigh conductivity and low capacitance, is placed into the fluid chamberabove the amplifier, as described below in more detail. The resultingplatform allows for improved high-frequency noise performance overtraditional measurements which rely on external electrophysiologyamplifiers such as the Axopatch 200B (available from Molecular DevicesInc.) or EPC-10 (available from HEKA Electronik GmbH). The CNP's planaramplifier design is also well suited to parallelization, and with theaddition of fluidics to isolate the trans chambers of an array ofnanopores, multi-channel detection can be supported by the platform (asdescribed in detail below).

While described herein with respect to CMOS integrated circuittechnology for the purpose of illustration and not limitation, thedisclosed subject matter can be used with any integrated circuittechnology, such as but not limited to CMOS, bipolar, SiGE, any node,and any other suitable integrated circuit technology known to one ofordinary skill in the art.

In one embodiment, a chip hosts a multi-channel preamplifier, such as an8-channel preamplifier with the topology shown in FIG. 6A (and thedetailed circuit description of FIG. 6B for the purpose of illustration.Each channel consists of a charge-sensitive preamplifier along with alow-noise transconductance to pass any DC current. A programmable activenegative capacitance is also included, which can extend the bandwidthbut does not decrease the input-referred noise. The transconductor iswired in a feedback loop which is tuned such that the overalltransimpedance gain has a similar first-order response to a classicalresistive-feedback stage with a gain of 100MΩ. The attenuator ‘1/A’ isdesigned as a filter with constant attenuation at signal frequencies buthigh gain at very low frequencies so that it suppresses DC offsets atthe output, improving dynamic range. The frequency response can be tunedby adjusting the loop gain through the gain stage G. Similar toclassical high-gain transimpedance amplifiers, the overall responsecannot be extended to arbitrarily high frequencies for stabilityreasons, and a simple filter stage (not shown) is cascaded with theamplifier output to restore its flat frequency response before beingdigitized. The value of C_(F) is programmable as 1 pF, 100 fF, or 50 fF,and the gain-bandwidth product of the OTA is 100 MHz. The total inputcapacitance of each channel is 1 pF+C_(F).

The chip can have any other circuitry in addition to the preamplifier.For example but not limitation, the chip can include data converters,digital signal processing, logic, memory, and/or any other suitablecircuitry known to one of ordinary skill in the art.

The 3×3 mm die can be produced in a standard 0.13 μm 1.5V mixed-signalprocess, with each preamplifier occupying approximately 0.3 mm² andconsuming 5 mW. Alternatively, the eight low-noise transimpedanceamplifiers each occupy 0.2 mm² and implement the circuit topology ofFIG. 2. While some of the results presented herein utilize only onechannel, however, the channels are independent and can be operated inparallel for continuous measurements of eight or more devices ifappropriate fluidics are implemented as described below. Furthermore,any suitable number of channels can be used. Several elements of aclassical transimpedance topology are adapted to make the designsuitable for modern integrated circuit technology. In particular, it isnecessary to achieve a well-defined high transimpedance gain without theavailability of high-value resistances. Purely capacitive feedback wouldbe appropriate if not for the significant DC bias currents of nanoporesensors. Thus in place of a traditional feedback resistor, the CNPimplements a DC servo loop with an active low-noise current source,producing a closed-loop circuit with a transimpedance gain of 100MΩ asshown in FIG. 7. A digitally selectable feedback capacitor C_(F) and thegain element G maintain loop stability by reducing the closed-loop gainabove 30 kHz, and the preamplifier is followed by a filter to restore aflat gain response to >1 MHz. The input stage is designed for negligiblegate leakage and a gate capacitance below 1 pF. When operated withC_(F)=0.15 pF, the preamplifier has a total input capacitance ofC_(I)=1.3 pF, voltage noise v_(n)=5 ηV/√Hz, and consumes 5 mW from a1.5V supply.

The preamplifier and fluid cell can be located on a 15-cm-by-13-cmprinted circuit board along with power regulation, biasing, and analogsignal paths. The board is powered by four AAA batteries and draws atotal of 30 mA, allowing a full day of continuous operation. Digitalcontrol interfaces are galvanically isolated, and signal outputs arefully differential. A second circuit board contains a four-pole Besselantialiasing filter as well as analog-to-digital converters and ahigh-speed USB interface.

In accordance with one aspect of the disclosed subject matter, thin-filmelectrodes (e.g. Ag/AgCl) are fabricated on the surface of the amplifierchip to enable a direct electrochemical interface between thepreamplifier and the electrolyte. With integrated amplifiers ofsub-millimeter dimensions, macro-scale electrodes can limit the density.Thus, fabrication on the surface of the chip in accordance with thedisclosed subject matter provides for small size and increasedscalability of the design. In accordance with a preferred embodiment,the electrode can be an Ag/AgCl microelectrode, which provides highperformance voltage-clamp measurements. However, additional electrodesthat can be used include, but are not limited to, platinum, gold,un-chlorinated silver, and other suitable electrodes known to one ofordinary skill in the art.

For example, in the exemplary 0.13 μm process used to fabricate the diethe top exposed metal is aluminum, which is unsuitable for chemicalenvironments. The aluminum is chemically etched away in phosphoric acid,exposing the adhesion and diffusion barrier layers beneath. Severalmicrons of silver can be deposited electrochemically from a platingsolution containing aqueous potassium silver cyanide (commerciallyavailable from Transene, Danvers, Mass.). The surface is then treatedwith ferric chloride to create a silver chloride coating on theelectrode. Images of this fabrication sequence are shown in FIGS. 8A-8Dfor the purpose of illustration. FIG. 8A shows the electrode as receivedfrom the foundry. FIG. 8B shows the exposed aluminum is chemicallyetched away. FIG. 5C shows several micros of silver are depositedelectrochemically. FIG. 8D shows the silver chlorinated with FeCl₃ tocreate an Ag/AgCl microelectrode. This process yields electrodes whichare stable operating with nanoampere-scale currents for several hours.

In accordance with some embodiments of the disclosed subject matter, atwo-chip stacked measurement cell is provided. The custom measurementcell allows discrete nanopore chips to be interfaced to the integratedpreamplifier having an electrochemically active surface electrode. Asillustrated in FIG. 9 for the purpose of illustration, a discretenanopore chip can be mounted in a Teflon fluid cell using KWIK-CASTsilicone adhesive (commercially available from World PrecisionInstruments, Sarasota, Fla.), and positioned immediately above theamplifier.

In this cell the trans reservoir is in direct contact with theamplifier's microelectrode, while a separate chlorinated silver wireserves as the cis electrode. Note that in contrast with the amplifierinput node, since this counterelectrode is only providing a DC voltagebias it is not significantly affected by any wiring parasitics.

In accordance with one aspect of the disclosed subject matter, DNAtranslocation events were measured in the two-chip configuration todemonstrate the amplifiers and integrated Ag/AgCl electrodes.Measurements were performed at a bias of 300 mV in a potassium chloridebuffer (e.g., 1M KCl, 1 mM EDTA, pH 8.0). Lambda DNA (commerciallyavailable from New England BioLabs, Ipswitch, Mass.) was added to thecis chamber, and the resulting current traces show an appropriatecharacteristic two-state transient response, as shown in FIG. 10 for thepurpose of illustration.

In accordance with some embodiments of the disclosed subject matter, asingle-chip nanopore and preamplifier chip integration and a process forpost-fabricating solid-state nanopores into the preamplifier chip areprovided. For example, during the design of the chip several 200×200 μmareas can be reserved for later fabrication of suspended dielectricwindows. In these areas of the chip, the metal routing layers areblocked, resulting in a thick stack of approximately 8 μm of alternatingglass fill and silicon nitride capping layers. The majority of thedielectric stack is etched from the front side using aninductively-coupled CHF₃+O₂ or SF₆ plasma, using evaporated chromium asa mask. After depositing and patterning a PECVD Si₃N₄ mask on the backof the die, the chip is mounted in a custom PDMS cell to protect thefront side features, and localized openings in the silicon substrate areetched anisotropically in heated 30% wt KOH. A short dip in bufferedhydrofluoric acid is then used to isolate a single 50 nm layer ofsilicon nitride from the original dielectric stack as a suspendedmembrane. Finally, nanopores are drilled through these nitride membraneswith a high resolution transmission electron microscope. A cross-sectionof the final window structure is illustrated in FIG. 11, and a TEM imageof one of these nanopores (having a thickness of about 6 nm in diameter)can be seen in FIG. 12. The design allows for the integration of foursolid-state nanopores per chip with the electronics surrounding eachpore as shown in the die photo of FIG. 12. However, more than fournanopores can be integrated on a single die the same size by reducingthe footprint for the pore electronics.

With no external input, the amplifiers show a measured input-referrednoise in good agreement with simulations, as shown in FIG. 13 for thepurpose of illustration. Noise spectral density at low frequencies isapproximately 12 fA/√Hz, comparable to a 110MΩresistor. At frequenciesabove 10 kHz, the noise is very sensitive to input capacitance, asexpected.

In accordance with some embodiments, a packaging of the single-chippost-processed integrated circuit to support electrolyte reservoirs oneither side of the chip is provided, as shown in FIG. 14 for the purposeof illustration. To isolate the potential at which the circuits operatefrom the electrolyte bias voltage, the circuits are implemented withtriple-well isolation. As part of post-processing, a backside insulatingpassivation layer is provided to prevent any electrochemicalinteractions between the substrate and the solution. This setup was usedto perform wet electrical measurements using external Ag/AgClelectrodes. For the purpose of illustration, FIG. 15 shows the resultsof DNA translocation experiments with 1M KCl and 20 ng/μL 15 kbp dsDNAat 100 mV bias.

In accordance with some embodiments of the single chip embodiment, the“top” Ag/AgCl electrode is integrated on the die by electroplating Agonto existing metal pads on the CMOS chip (as shown in FIG. 14). Todrive C_(MEMBRANE) below 1 pF, access of the electrolyte to the chip canbe reduced to 250-μm-by-250-μm, combined with a 15-μm-by-15-μm nitridewindow. The presence of back-end interconnect layers in the chipprovides a dielectric stack 8-μm thick (FIG. 11), yielding a capacitanceof only 4.4 pF/mm². The membranes in the vicinity of the pore can bethinned to be less than 10 nm, further improving signal levels. Theseultra-thin membranes will help to improve the spatial resolution ofnanopore devices, combined with the fast temporal resolution uniquelyenabled by the integrated electronics. As shown in FIG. 14, the chippackaging also includes a ball-grid-array package and printed-circuitboard to accommodate the wet environment. Of note, using an externalelectrode for the “bottom” Ag/AgCl electrode does not degrade thenoise-limited bandwidth for detection since only capacitances on theamplifier side of the pore shape the noise.

For the purpose of illustration and not limitation, FIG. 16 is a plot ofthe total RMS current noise that can be expected in several scenarios.The tolerable noise level depends on the signal being measured, but forreasonable solid-state nanopore sensing scenarios the noise-limitedbandwidth can be defined as the bandwidth at which the noise is largerthan 100 pA_(rms). Scenario A approximates the current state-of-the-artfor solid-state nanopores, as measured by a discrete amplifier withC_(IN)=15 pF, C_(WIRING)=10 pF, and C_(MEMBRANE)=60 pF. For example, theAxopatch 200B patch clamp amplifier (Molecular Devices, Sunnyvale,Calif.) is a low-noise instrument which has been improved forelectrophysiology applications that have similar constraints as nanoporesensors. However, as discussed previously, at frequencies aboveapproximately 10 kHz the primary factor determining the amplifier noisedensity is the total input capacitance. On this metric, a discreteamplifier cannot compete with an integrated solution. Additionally, animmediate practical concern is that the Axopatch does not support signalfrequencies higher than 100 kHz. Scenario B estimates the lowest noisethat could likely be achieved with a discrete amplifier by reducingC_(MEMBRANE) to 1 pF while C_(IN) and C_(WIRING) remain the same. Whilethis represents a several-fold improvement over today's state of theart, the useful bandwidth is still constrained by wiring and amplifierparasitics. Scenario C simulates the additional benefit of using anintegrated amplifier with C_(IN)=1 pF and C_(WIRING)=0. Trace D plotsthe measured input noise floor of a preamplifier in accordance with thedisclosed subject matter with no pore connected(C_(MEMBRANE)=C_(WIRING)=0). As can be seen, an integrated solutionusing a preamplifier in accordance with the disclose subject matter issuperior to methods using known amplifiers.

For the purpose of illustration and not limitation, FIG. 17 shows thenoise-limited bandwidth for a signal level of 1 nA, comparingmeasurement with the Axopatch to measurement with the integratedamplifier in accordance with the disclosed subject matter as a functionof C_(MEMBRANE). For C_(MEMBRANE)<1 pF, bandwidths in excess of 1 MHzcan be achieved for integrated amplifiers in accordance with thedisclose subject matter.

Nanopore signal fidelity is extremely sensitive to parasitic electronicelements at the amplifier input, including any capacitance arising fromthe pore membrane (FIG. 1). Silicon nitride nanopores are fabricated inthin suspended dielectric windows on silicon substrates, and C_(M) canbe modeled as a parallel-plate capacitance of the constituent elementsof C_(M)=Σ_(i)∈₀∈_(r)A_(i)/d_(i), where ∈ is the permittivity of freespace, ∈_(r) is the relative permittivity of the dielectric, A_(i) isthe area of fluid contact with the membrane substrate, and d, is thethickness of the dielectric. Early solid-state nanopores had values ofC_(M) larger than 300 pF. For the nanopores utilized in accordance withthe disclosed subject matter (FIG. 5), a 50×50 μm suspended 25 nmsilicon nitride window is supported by a 5 μm thermal SiO₂ layer whichsignificantly reduces C_(M). Additionally, in the course of mounting thenanopore to the fluid cell, the surface of the membrane chip is coveredwith a silicone elastomer, leaving only a minimal area exposed to theelectrolyte. As a result, C_(M) is reduced to less than 6 pF fornanopores in accordance with the disclosed subject matter (FIG. 5). Withfurther fabrication efforts, C_(M) can be reduced below 0.5 pF.

The close integration of the measurement electronics also reduces wiringcapacitance (C_(W)). In platforms with external amplifiers, C_(W)results from any capacitive coupling to other nodes (typically greaterthan 2 pF) from the short length (<10 cm) of wire which connects oneAg/AgCl electrode to the amplifier input. The use of unshielded wires(chosen to reduce parasitic capacitance) necessitates performingmeasurements in a Faraday cage to reduce electromagnetic interference.In the CNP design, the distance between an Ag/AgCl surface electrode andthe amplifier input can be less than 100 μm and there are minimalrequirements for external shielding. The presence of the electroniccircuitry immediately adjacent to the fluid chamber, however, means thatthe ions in the electrolyte can capacitively couple to the metal wiringof the integrated circuits. To minimize this effect, the surface of theamplifier chip is covered with 200 μm-thick SU-8 in all areas outsidethe electrode. This augments the 6 μm of passivation dielectric presentby default on the chip surface. The resulting C_(W) is less than 1 pF.

In accordance with some embodiments, a method for fabrication andpackaging multiple pores on the same chip is disclosed. For example,multiple pores can be formed in the one-chip topology shown in FIG. 14in which nanopores are integrated directly into the die with fluidics oneither side of the chip. One approach for integrating multiple pores isshown in FIG. 18 for the purpose of illustration and not limitation. Inthis case, wells of SU-8 photoresist can be used to isolate individualnanopores from each other. In this case, since electrical isolation isnecessary between the multiple cis reservoirs, a PDMS cap can be used toseal the wells for measurement after the introduction of reagents asshown in FIG. 18. In accordance with this method the full integration of64 nanopores onto the same 5-mm-by-5-mm die can be provided. In anotherembodiment, a two-chip multi-well implementation using the same CNPdesign is provided, as shown in FIG. 19 for the purpose of illustrationand not limitation.

In some embodiments, the CNP platform in accordance with the disclosedsubject matter also allows the integration of biological nanopores.While solid-state pores have distinct advantages in manufacturabilitythat is compatible with electronics processing (which was exploited asdescribed above) and high pore signal levels, biological nanopores,including but not limited to alpha-Hemolysin (αHL) or MspA, have severaldistinct advantages, including high reproducibility and slower DNAtranslocation rates due to stronger DNA-pore interactions.

In some embodiments, the biological nanopores can be created in lipidmembranes (typically 1,2-diphytanoyl-sn-glycero-3-phosphocholine(DPhPC)) formed over a hole in a hydrophobic membrane between two fluidcells. The conductance between the two chambers of the cell is monitoredwhile the membrane protein is added to one of the wells, which is thenimmediate flushed once incorporation is detected.

The dielectric membranes described above can also be used as solidsupports for lipid bilayers with the creation of moderately largerholes, over which the lipid bilayer is formed. For example, planarbilayer lipid membranes (BLMs) have been engineered with differentprotein channels on patterned solid supports with nanopatterned holes(˜100 nm in diameter), as well as tethering BLMs directly onto goldsurfaces through a self-assembled monolayer assembly.

To study the contiguousness of these bilayer films, the fluorescentrecover after photobleaching (FRAP) technique was used. Fluorescein-DHPEwas dried along with the DOPC, before reconstitution in water at 2.5mg/ml, after which they were extruded through porous membranes to form50-100 nm diameter unilamellar vesicles. FIG. 20 c shows some of theresults of these FRAP studies. The studies indicate the formation ofcontiguous BLMs with a diffusion coefficient of 4 μm²/s on nanopatternedsubstrates, and BLMs formed on SAM-gold assemblies with a coefficient of0.8 μm²/s. Both fall within the ideal diffusion range of 0.1-10 μm²/srepresentative of well-formed BLMs. Electrical characterizations ofthese BLMs indicate a high impedance membrane with a 1.4 GΩ-mm²resistance, suitable for further electrical analysis of biologicalnanopores formed in the membranes.

For the purpose of illustration and not limitation, FIG. 20 shows theintegration of biological nanopores using the CNP platforms describedabove with holes in dielectric membranes by building lipid bilayers onthe surface of the CNP designs. The protein nanopore formed over thenitride membrane approach to be employed here is shown in FIG. 20 a. Inthis case, slighter larger holes will be formed in the silicon nitridemembrane (on the order of 100-250 nm) than were used for direct nanoporeintegration described above. αHL can be used, monitoring the conductanceduring incorporation to ensure single channel introduction, andimmediately washing after channel formation. For fabricating multiplechannels on the same chip, a voltage bias can be used to slow downincorporation, which can allow the bias to dynamically change afterincorporation in an individual channel to prevent multipleincorporation.

In accordance with some embodiments, the integration of biologicalchannel proteins using the CNPs platform described above with tetheredBLMs is provided. The protein nanopore formed over a SAM approach to beemployed here is shown in FIG. 20 b. In this case, the surface electrodeis post-processed with a gold coating rather than silver, and isfunctionalized with a self-assembled monolayer (SAM), which provides analternative surface for fluid lipid bilayer formation. Alkanethiols areone such material that readily forms SAMs on gold, producing a substratethat is both electrically conducting and conducive for lipid bilayerformation. Proteins within planar lipid bilayers can be formed on aSAM-gold assembly. In this arrangement there need not be electrolyte onthe back side of the chip; the trans reservoir will be the liquidconfined between the lipid bilayer and the gold surface, while the cisreservoir will be on the top side of the BLM.

In accordance with some embodiments, a “two-chip” biological nanoporeembodiment is provided. Such an embodiment is similar to the two-chipsolid-state nanopore embodiment described above and shown in FIG. 9, butthe membrane is a self-assembled lipid bilayer instead of a dielectricmaterial. In one embodiment, the lipid bilayer is in contact with thesurface of the integrated circuit chip.

In accordance with one aspect of the disclosed subject matter, themembrane can be any suitable membrane, such as but not limited to asilicon nitride or graphene membrane. Graphene membranes are very thinpore substrate and can probe at subnanometer length scales. The pore canbe fabricated using any known technique such as through electron-beamablation, which allows pores to be reliably and repeatably made todiameters as small as 2 nm.

As described above, an integrated preamplifier for nanopore sensors inaccordance with the disclosed subject matter significantly reduceselectrical parasitics present in measurements with external amplifiers.The new arrangement can extend the useful bandwidth of nanopore sensorsbeyond 1 MHz, as compared to today's limits of sub-100 kHz measurements.Such bandwidths are highly relevant to achieve the time resolutionuseful for DNA sequencing with nanopores. For example, single-moleculeevents as short as Its can be observed. Additionally, the monolithicintegration of solid-state nanopores into a commercial CMOS die canprovide ultrasensitive single-molecule biosensing applications.

Furthermore, the use of integrated preamplifier for nanopore sensors inaccordance with the disclosed subject matter significantly reduces thecost and size as compared to the use of known external amplifiers. Forexample, the superior electrical performance is obtained with anintegrated amplifier that consumes an area of only 0.2 mm² on a CMOSchip compared with a rack-mounted >10-kg Axopatch amplifier. At the sametime, an Axopatch can cost more than about $25,000 while the amplifierproposed here could cost about $0.10 in volume manufacturing.

While the above disclosed subject matter focused on the measurement ofthe conductance of the pore, one of ordinary skill in the art willrecognize that other sensing modalities are conceivable. For example butwithout limitation, monitoring tunneling currents with transverseelectrodes, measuring capacitances through nanoelectrodes, and measuringconductance of graphene nanoribbons or carbon nanotubes positioned inclose proximity to pores can also benefit from the integratedmeasurement electronics described herein. Measuring the ionicconductance of other transmembrane proteins is another application ofthe disclosed subject matter. Additional opportunities presented by thehigh-bandwidth bioelectronic interfaces described herein include theability to study fast reaction kinetics, single-molecule transportphenomena, or fast conformational changes of macromolecules.Single-molecule recapture systems or closed-loop electrostatic trapswould similarly benefit from high-bandwidth sensing.

EXAMPLES CMOS-Integrated Nanopore Platform (CNP)

The amplifier is a custom integrated circuit implemented using acommercial IBM 0.13 μm bulk CMOS mixed-signal process. The amplifier dieis wirebonded to a 272-pin ball-grid array (BGA) package. Dam-and-filldoughnut epoxy encapsulation (available commercially as Hysol FP4451 damand FP4650 fill) covers the exposed gold wirebonds, leaving the diesurface exposed.

After doughnut encapsulation, the chip surface is further passivatedwith SU-8. Under yellow light, a drop of SU-8 2015 (commerciallyavailable from Microchem) is manually applied to the surface of theamplifier die, filling the 300 μm-deep cavity formed by the epoxy dam. Alight vacuum is applied in a dessicator for 15 minutes, followed by anovernight prebake in an oven at 80° C. The chip is exposed in an MJB-3UV contact aligner using a chrome-on-glass mask, 2,000 mW/cm² dose, and360 nm long-pass UV filter (commercially available from Omega Optical).A post-exposure-bake for 30 min at 50° C. and development in SU-8Developer (commercially available from Microchem) yields a layer of SU-8approximately 200-300 μm thick with 300 μm square openings surroundingthe 100×100 μm square electrodes.

A watertight fluid chamber is constructed by fastening a 1-cm segmentfrom a polypropylene tube to the top of the BGA package using PDMS(commercially available as Sylgard 184, Dow Corning). Additionally,KWIK-CAST (commercially available from World Precision Instruments) isapplied on the die surface leaving only one amplifier channel exposed.

After packaging the die, the aluminum is etched from the exposed surfaceelectrodes by pipetting 500 μL of Aluminum Etchant Type A (commerciallyavailable from Transene, Danvers, Mass.) into the fluid chamber forseveral minutes, followed by multiple rinses with DI water.

The chip is mounted on a circuit board, power is applied, and digitallogic is applied which shunts the amplifier's feedback element, C_(F),clamping the electrodes at a constant voltage and providing a path forit to sink several microamperes of current. A small volume (˜1 mL) ofsilver electroplating solution containing potassium silver cyanide(available from Transene, Danvers, Mass.), is added to the fluidchamber, and a silver wire counterelectrode is attached to a Keithley2400 I-V meter and placed in the solution. The voltage is adjusted toachieve a counterelectrode current of 1 μA for several minutes,resulting in a deposition of approximately 10 microns of silver onto theelectrode. After electroplating, the chamber is rinsed multiple timeswith deionized water.

The silver microelectrodes are converted to Ag/AgCl pseudo-referenceelectrodes by applying a drop of 10 μL 50 mM FeCl₃ to the surface for 30seconds. After several hours of experiments, the chlorination typicallyneed to be repeated. The chlorination can be repeated several timesbefore the silver electrode is exhausted.

Nanopores in ultrathin silicon nitride membranes are fabricated as knownin the art. Briefly, a 500 μm thick <100> silicon wafer with 5 um ofthermal oxide is coated with 25 nm of low-stress LPCVD SiN. Standard UVphotolithography is used to pattern square openings on one side of thewafer, through which the SiO₂/SiN is etched using SF₆ plasma. Thephotoresist is stripped, and an anisotropic KOH etch followed by removalof the SiO₂ layer results in ˜50×50 μm free-standing windows on thereverse side of the wafer.

A film of PMMA is spun onto the membrane side of the window, andelectron-beam lithography is used to pattern a small 200×200 nm squareopening. A SF₆ plasma etch locally thins the SiN to approximately 10 nm.The PMMA is removed by incubation in acetone. A single nanopore isdrilled through the thinned region of the nitride membrane using a JEOL2010F HR-TEM.

The nanopore chip is cleaned in piranha acid using a procedure known inthe art. After rinsing and drying the membrane, it is immediatelymounted onto a custom Teflon fluid cell using KWIK-CAST (available fromWorld Precision Instruments). Additionally, KWIK-CAST is carefullypainted over the majority of the membrane-facing side of the chip,leaving an exposed <1 mm² area around the membrane (see FIG. 5 e).

When testing with the Axopatch 200B, the Teflon cell is placed into amating fluid cell containing 1M KCl 10 mM Tris buffer, pH 8.0. Inside aFaraday cage, two homemade Ag/AgCl pellet electrodes are connected tothe headstage input and ground, respectively.

For testing with the CNP amplifier, the circuit board is placed in smallaluminum box and the lower (trans) reservoir is filled with 500 uL 1MKCl, pH 8.0. The upper (cis) chamber within the Teflon cell is filledwith 200 uL electrolyte, and the cell is placed into the amplifierchamber. An Ag/AgCl pellet electrode is placed in the cis chamber. Theamplifier input voltage is held constant, while the DC potential of theopposing electrode is varied to apply a bias across the nanopore.

The preamplifier with its attached fluid chamber is mounted in acompression-mount BGA socket (commercially available from EmulationTechnologies) on a 15×13 cm circuit board, and placed in a smallaluminum box. The circuit board contains DC voltage regulation, biasingcircuitry, analog signal buffering and filters, all of which arecarefully designed for low-noise operation. This preamplifier board ispowered from four AAA batteries and its digital interfaces aregalvanically isolated. A second interface board outside the aluminum boxhosts digital isolators, antialiasing filters (4-pole differentialBessel filter, f_(c)=1 MHz) and data converters (operating at either 2.5MS/s or 4 MS/s), as well as an FPGA module (commercially available asOpal Kelly XEM3010) with a high-speed USB interface. The dataacquisition and control of the system is managed in real-time through agraphical interface written in Matlab.

The data is processed using Matlab software. Traces are generallydigitally filtered with a 128-tap finite-impulse-response low-passfilter to a desired signal bandwidth, while retaining the 2-4 MS/ssample rate. Events are typically identified with a two-statethresholding algorithm in Matlab, but for traces with low SNR, amodified algorithm is used to identify the events. First, samples areidentified whose value is more than 5 standard deviations below the meanopen pore current. Next, a local search finds the nearest sample pointsat which the current is above the open pore current. Finally, event edgetimes are assigned at the first and last points within these bounds thatthe signal is more than 4 standard deviations from the baseline current.

Noise Measurements in CMOS-Integrated Nanopore Platform (CNP)

The measured open-headstage noise spectrum of the CNP system (C_(F)=0.15pF, 1 MHz 4-pole Bessel filter, f_(s)=4 MS/s) is shown in FIG. 21 a,alongside a measurement of the baseline noise for a comparableconfiguration of the Axopatch 200B (whole-cell mode with β=1, 100 kHz4-pole Bessel filter, f_(s)=250 kS/s). At measurement bandwidths below10 kHz, the noise of the Axopatch is lower than the CNP, owing to the 10fA/√Hz current noise of the CNP's on-chip current source (FIG. 7) ascompared to 5.7 fA/√Hz from a discrete 500MΩ feedback resistor in theAxopatch. However, for B>10 kHz, the CNP delivers significantly lowernoise floors. For the highest bandwidth supported by the Axopatch (B=100kHz), the CNP has a noise floor of 3.2 pA_(RMS), compared to 9 pA_(RMS)for the Axopatch. At the highest bandwidth characterized for the CNP(B=1 MHz), the noise level is 24 pA_(RMS), in contrast with 247 pA_(RMS)modeled by extrapolating the Axopatch response beyond its supportedrange.

When a nanopore is connected to the amplifier input, the introduction of1/f noise and membrane capacitance raises the noise spectrum above theopen-headstage baseline, as shown in FIG. 21 b (a polynomial fit is alsoshown to i_(n) ²=A/f+B+Cf+Df², where f is the frequency (Hz) and A, B,C, and D are fitting parameters). Approximately 15 solid-state nanoporeswere measured with the CNP and significant pore-to-pore SNR variabilitywas observed, due both to variations in the pore geometry and in C_(M).In the discussions that follow, data from two representative poredevices (“PoreA” and “PoreB”) are selected for analysis. PoreA (d=4.9nm, C_(M)=6 pF, ΔI=882 pA at 400 mV) has lower membrane capacitance thanPoreB (d=3.5 nm, C_(M)=25 pF, ΔI=840 pA at 400 mV). FIG. 21 c showsroot-mean-squared (RMS) current noise as a function of bandwidth,corresponding to the signals in the plot of FIG. 21 a and FIG. 21 dshows the RMS current noise corresponding to the signal in FIG. 21 balong with measured RMS current noise for a similar nanopore measuredwith the Axopatch 200B with the same configuration as FIG. 21 a. FIGS.21 e and f are current traces corresponding to the points in FIGS. 21 cand d.

For the lowest-capacitance devices measured, such as PoreA, noise levelsin the CNP are demonstrated at 12.9 pA_(RMS) and 155 pA_(RMS) forbandwidths of 100 kHz and 1 MHz, respectively (FIG. 21 f). Measuredcomparisons are shown with the Axopatch up to 100 kHz. For B=100 kHz,there is more than a factor-of-two reduction in input-referred noisepower for the CNP. If the Axopatch could be measured at higherbandwidths, there would be a factor-of-six noise power difference at 1MHz.

Aside from the overall lower noise at high frequencies, polynomial fitsto the noise power spectrum (FIG. 21 b) are notable for the absence of asignificant linear component at moderate frequencies (>1 kHz), whichdominate the high-frequency noise in earlier reports. A linear spectralcomponent can have several possible sources, but the CNP's improvementis likely due to the high-quality dielectric properties of the thermalSiO₂ passivation of the nanopore support chip.

Maximizing Signal Strength in CMOS-Integrated Nanopore Platform (CNP)

Maximizing the SNR involves both minimizing noise and maximizing theamplitude of the signal. The measured current signal is given byΔI=V_(BIAS)ΔG, where V_(BIAS) is the applied bias and AG is the changein ionic conductivity caused by the presence of a molecule. Recentresults with thin silicon nitride nanopores demonstrate current pulsesfrom dsDNA as large as 4 nA using 4-nm-diameter pores in 8-nm-thickmembranes at 300 mV bias.

For the measurements presented here, free-standing 25-nm-thick siliconnitride membranes are locally thinned using an SF₆ plasma, yieldingsmall membrane regions approximately 10-15 nm thick. A single nanoporeis fabricated in a thinned region using a transmission electronmicroscope. Fabricated pores ranged from 2-6 nm in diameter, but thebest signals were obtained for 3.5-4 nm pores. All experiments wereperformed using 1M KCl buffered with Tris to pH 8.0.

FIG. 21 g and h shows plots of SNR (as introduced above) for both PoreAand PoreB as a function of measurement bandwidth. For PoreA, C_(M)=6 pFand ΔI=814 pA (400 bp DNA, 300 mV, N=330). For PoreB, C_(M)=25 pF andΔI=840 pA (50 bp DNA, 400 mV, N=2,974). As dwell times varysignificantly, the SNR is shown for a range of 1 μs<τ<∞. For PoreA, SNRis maintained above 10 beyond 600 kHz measurement bandwidth, and above 5beyond 1 MHz. For PoreB, SNR values of 10 and 5 are maintained up to 160kHz and 320 kHz, respectively. FIG. 21 i, which plots B_(MAX) for SNR>5as a function of signal amplitude ΔI, shows that in the limit of verysmall C_(M), the baseline amplifier noise floor corresponds to usablemeasurement bandwidth of several MHz.

Short DNA Measurements

As an example of the short timescales observable with the CNP, FIG. 22shows a current trace measured for PoreB with 25 bp dsDNA. The pore wasbiased at 600 mV, digitized at 2.5 MS/s, and then digitally filtered toboth 500 kHz (blue) and 100 kHz (red) bandwidths. The 500 kHz tracerepresents the maximum bandwidth in which SNR>5 for PoreB in theseconditions (ΔI=1.3 nA, N=1,307), and the 100 kHz trace is included as acomparison to the supported bandwidth of alternative platforms. In the0.5-second trace shown, 29 pulses are visible, ranging in duration from1.2 μs to 30.2 μs. Points are recorded at intervals of 0.4 μs but therise and fall times are approximately 1 μs and 5 μs for the 500 kHztrace and 100 kHz trace, respectively. Accordingly, events shorter than10 μs are clearly visible in the 500 kHz trace but their amplitude isattenuated at 100 kHz. Notably, the data presented here was taken atroom temperature.

DNA Translocation Statistics

Extended signal bandwidth also gives the ability to consider thestatistics of shorter duration events than have been previouslyobserved. At 3.5 nm in diameter, PoreB is small enough that oligomertranslocation times are dominated by surface interactions rather thanelectrophoretic forces. As such, a wide variance in translocation timesis observed. FIG. 23 shows a dataset of the durations and depths ofevents seen for 50 bp DNA at 250-450 mV bias, for both 400 kHz (blue)and 100 kHz (red) signal bandwidths. FIG. 23 a shows the event rate as afunction of applied bias. The event rate scales roughly linearly above a200 mV threshold, suggesting a diffusion-limited capture regime. Eventrates are similar for the two bandwidths except that at 100 kHz someevents are lost at high bias (due to filtering), while at 400 kHz someevents are lost at low bias (due to noise). FIG. 23 b shows the mostprobable dwell time as a function of applied potential. Events becomefaster with higher bias but measured dwell times saturate near thetemporal resolution of the selected filters. FIG. 23 c shows histogramsof events at applied potentials from 250-450 mV, for the two bandwidths.FIG. 23 d is a scatter plot of events observed at 450 mV bias. Eventsshorter than 10 μs are severely distorted and attenuated by a 100 kHzmeasurement bandwidth.

Observed event rates for the two bandwidths are similar, showing aroughly linear trend with bias voltage, above a threshold of 200 mV.However, the event durations decrease with applied bias, and events asshort as 2 μs are clearly distinguished at 400 kHz, while at 100 kHzevents shorter than 10 μs are strongly attenuated and their apparentdwell time saturates near the temporal response of the filter. Thisdistortion has a marked effect on the observed statistics of the events,exaggerating the duration of short events in the 100 kHz dataset (FIG.23 b-c). At 400-450 mV, events continue to be observed below the 2.5 μsresponse of the 400 kHz filter, implying the existence ofsub-microsecond events which could be observed if the membranecapacitance of PoreB were further decreased.

Intra-Event Translocation Dynamics

At low bandwidths and sample rates, nanopore-DNA interactions can appearto have uniform blockade levels, but in a number of cases events havebeen observed with multiple current levels which correspond to foldedpolymers, hybridized probe molecules, or conformations of largerproteins. Statistical analyses of the durations of nanopore events haveshown that within the typical operating range of these sensors, severaldifferent biophysical processes can be observed. For larger nanopores,translocation times can be dominated by electrophoretic forces, whilefor smaller-diameter pores it can take longer for a polymer to diffuseinto a proper orientation for an end to be threaded through the pore.The event duration can be further extended by physiochemicalinteractions between the molecule and the pore surface.

FIG. 24 presents a dataset of events measured for PoreB with 50 bp DNAfragments at 500 mV bias. FIG. 24 a is an illustration of the sequentialprocesses of nanopore translocation. First a molecule diffuses near thepore, where it is captured by the electric field. The molecule istrapped at the mouth of the pore until it finds a conformation whichallows one of its ends to thread through the pore. FIG. 24 b showstypical signals observed for 50 bp dsDNA fragments with PoreB (3.5 nm)at 500 mV bias. The events have a characteristic shallow level followedby a deeper tail. FIG. 24 c is histogram of ΔI event depths (N=3955) for50 bp DNA at 500 mV bias. The depth of the whole events and the depth ofthe last 2 μs of each event have distinct distributions. FIG. 24 d is aplot of the most probable ΔI for whole events, along with the mostprobable ΔI for the first and last 2 μs of an event. The depth of thelast 2 μs retains a linear relationship with voltage up to 500 mV, whilethe earlier sections of the event become shallower at high bias. Thiscan be indicative of molecular dynamics at high electric fields whichsuppress polymer diffusion and extend the duration of the ‘Capture’phase relative to the ‘Threading’ phase.

For this high bias, events are commonly observed to have acharacteristic shallow blockage level, followed by a deeper tailimmediately before completion. This bears a strong resemblance tosignals previously observed for hairpin DNA molecules with proteinnanopores. One reasonable explanation for this intra-event structure isthe multi-state process illustrated in FIG. 24 a. A diffusing moleculeis captured by the nanopore, but the strong electric field andrelatively stiff molecule (a 50 bp DNA molecule is approximately 15 nmlong, with a radius of curvature of 4 nm) prevent the molecule fromquickly finding an appropriate conformation to thread through the 3.5 nmnanopore. The presence of the molecule trapped at the mouth of thenanopore causes the initial shallow blockage. When the moleculeeventually threads successfully, it translocates to the opposingchamber, causing a deeper blockage.

In this dataset the duration of the deeper tail is often less than 10is, and it is commonly obscured in lower-bandwidth measurements. Therelative depth of the tail can be analyzed statistically by consideringa histogram of the mean depths of each whole event, as compared to thedepth of last 2 μs of each event. As shown in FIG. 24 c, these blockagelevels show markedly different distributions, with centers at 0.75 nAand 1.1 nA, respectively. Interestingly, the depth of the last 2 μsshows a more linear relationship with bias voltage than does the depthof events as a whole (FIG. 24 d). This supports that the tailcorresponds to the translocation of a molecule, and that at lower biasvoltages the ‘capture’ state is simply too short to contributesignificantly to observed events.

While the disclosed subject matter is described herein in terms ofcertain embodiments, those skilled in the art will recognize thatvarious modifications and improvements can be made to the applicationwithout departing from the scope thereof. Thus, it is intended that thepresent application include modifications and variations that are withinthe scope of the appended claims and their equivalents. Moreover,although individual features of one embodiment of the application can bediscussed herein or shown in the drawings of one embodiment and not inother embodiments, it should be apparent that individual features of oneembodiment can be combined with one or more features of anotherembodiment or features from a plurality of embodiments.

In addition to the specific embodiments claimed below, the disclosedsubject matter is also directed to other embodiments having any otherpossible combination of the dependent features claimed below and thosedisclosed above. As such, the particular features presented in thedependent claims and disclosed above can be combined with each other inother manners within the scope of the application such that theapplication should be recognized as also specifically directed to otherembodiments having any other possible combinations. Thus, the foregoingdescription of specific embodiments of the application has beenpresented for purposes of illustration and description. It is notintended to be exhaustive or to limit the application to thoseembodiments disclosed.

1. A method for detecting a single-molecule using an integrated circuitwhich includes at least one membrane having a nanopore located betweenfirst and second reservoirs and a low-noise preamplifier having anelectrode formed on the surface thereof, comprising: passing a targetmolecule through the nanopore; and measuring a current through thenanopore to detect the presence of a biomolecular entity, if any.
 2. Themethod of claim 1, wherein the preamplifier comprises a low-noisemulti-channel CMOS preamplifier.
 3. The method of claim 1, wherein theelectrode is selected from the group consisting of Ag/AgCl, platinum,gold, and un-chlorinated silver.
 4. The method of claim 1, wherein thenanopore is positioned on a silicon chip adjacent to the preamplifier.5. The method of claim 1, wherein the nanopore comprises a nanoporedirectly integrated onto the preamplifier.
 6. The method of claim 5,wherein the first and second reservoirs are located on opposite sides ofthe preamplifier.
 7. The method of claim 1, wherein the nanoporecomprises a solid state nanopore.
 8. The method of claim 1, wherein thenanopore comprises a biological nanopore.
 9. The method of claim 8,wherein the membrane is a lipid bilayer.
 10. The method of claim 1,wherein the electrode is in direct contact with one of the first andsecond reservoirs.
 11. The method of claim 1, wherein the integratedcircuit comprises a plurality of nanopores.
 12. An integrated circuitfor single-molecule detection, comprising: at least one membrane havinga nanopore located between first and second reservoirs; a low-noisepreamplifier for measuring the change in pore current upon passing atarget entity through the nanopore, wherein the preamplifier has atleast one electrode formed on the surface thereof.
 13. The integratedcircuit of claim 12, wherein the preamplifier comprises a low-noisemulti-channel CMOS preamplifier.
 14. The integrated circuit of claim 12,wherein the electrode is selected from the group consisting of Ag/AgCl,platinum, gold, and un-chlorinated silver.
 15. The integrated circuit ofclaim 12, wherein the nanopore is located through a silicon chipadjacent to the preamplifier.
 16. The integrated circuit of claim 12,wherein the nanopore comprises a nanopore directly integrated onto thepreamplifier.
 17. The integrated circuit of claim 16, wherein the firstand second reservoirs are located on opposite sides of the preamplifier.18. The integrated circuit of claim 12, wherein the nanopore comprises asolid state nanopore.
 19. The integrated circuit of claim 12, whereinthe nanopore comprises a biological nanopore.
 20. The integrated circuitof claim 19, wherein the membrane is a lipid bilayer.
 21. The integratedcircuit of claim 12, wherein the electrode is in direct contact with oneof the first and second reservoirs.
 22. The integrated circuit of claim12, wherein the integrated circuit comprises a plurality of nanopores.